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DATA SHEET
MOS INTEGRATED CIRCUIT
PD6P5
4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
The PD6P5 is a microcontroller for infrared remote control transmitters which is provided with a one-time PROM as the program memory. Because users can write programs for the PD6P5, it is ideal for program evaluation and small-scale production of the application systems using the PD64A or 65. When reading this document, also refer to the PD64A, 65 Data Sheet (U14380E).
FEATURES
* Program memory (one-time PROM) : 2,026 x 10 bits * Data memory (RAM) * 9-bit programmable timer * Command execution time * Stack level * I/O pins (KI/O) * Input pins (KI) * Sense input pin (S0, S2) * S1/LED pin (I/O) * Power supply voltage * Operating ambient temperature * Oscillator frequency * POC circuit : 32 x 4 bits : 1 channel : 16 s (when operating at fX = 4 MHz: ceramic oscillation) : 1 level (Stack RAM is for data memory RF as well.) : 8 units : 4 units : 2 units : 1 unit (In output mode, this is the remote control transmission display pin.) : VDD = 2.2 to 3.6 V : TA = -40 to +85 C : fX = 2.4 to 4.8 MHz * Built-in carrier generation circuit for infrared remote control
APPLICATION
Infrared remote control transmitter (for AV and household electric appliances)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14760EJ1V0DS00 (1st edition) Date Published May 2000 J CP(K) Printed in Japan
(c)
2000
PD6P5
ORDERING INFORMATION
Part Number Package 20-pin plastic SSOP (7.62 mm (300))
PD6P5MC-5A4
PIN CONFIGURATION (TOP VIEW)
20-pin Plastic SSOP (7.62 mm (300)) * PD6P5MC-5A4 (1) Normal operation mode
KI/O6 KI/O7 S0 S1/LED REM VDD XOUT XIN GND S2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
2
Data Sheet U14760EJ1V0DS00
PD6P5
(2) PROM programming mode
D6 D7 CLK (L)
1 2 3 4 5
20 19 18 17 16 15 14 13 12 11
D5 D4 D3 D2 D1 D0 MD3 MD2 MD1 MD0
VDD XOUT XIN GND VPP
6 7 8 9 10
Caution Round brackets ( ) indicate the pins not used in the PROM programming mode. L: Connect each of these pins to GND via a pull-down resistor.
BLOCK DIAGRAM
REM
CARRIER GENERATOR
4 CPU CORE ONETIME PROM
PORT KI
4
KI0-KI3
8
PORT KI/O
8
KI/O0-KI/O7
S1/LED
9-bit TIMER
2
PORT S
2
S0, S1/LED, S2
RAM
SYSTEM CONTROL
XIN XOUT VDD GND
Data Sheet U14760EJ1V0DS00
3
PD6P5
LIST OF FUNCTIONS
Item ROM capacity 2,026 x 10 bits One-time PROM RAM capacity Stack I/O pin 32 x 4 bits 1 level (shared with RF of RAM) * Key input (KI) * Key I/O (KI/O) * Key expansion input (S0, S1, S2) * Remote control transmitter display output (LED) Number of keys * 32 keys * 56 keys (when expanded by key expansion input) Clock frequency Ceramic oscillation * fX = 2.4 to 4.8 MHz Instruction execution time Carrier frequency Timer POC circuit Supply voltage Operating ambient temperature Package * 20-pin plastic SSOP (7.62 mm (300)) 16 s (at fX = 4 MHz) fX/8, fX/16, fX/64, fX/96, fX/128, fX/192, no carrier (high level) 9-bit programmable timer Provided VDD = 2.2 to 3.6 V * TA = -40 to +85 C : 1 channel : 4 pins : 8 pins : 3 pins : 1 pin (shared with S1 pin)
PD6P5
4
Data Sheet U14760EJ1V0DS00
PD6P5
TABLE OF CONTENTS
1. PIN FUNCTIONS .........................................................................................................................
1.1 1.2 1.3 1.4 1.5 Normal Operation Mode .................................................................................................................... PROM Programming Mode ............................................................................................................... INPUT/OUTPUT Circuits of Pins ...................................................................................................... Dealing with Unused Pins ................................................................................................................ Notes on Using KI Pin at Reset ........................................................................................................
6
6 7 8 9 9
2. DIFFERENCES AMONG PD64A, 65, AND PD6P5 ................................................................ 10
2.1 Program Memory (One-time PROM) ................................................................................................ 11
3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................. 12
3.1 3.2 3.3 Operation Mode When Writing/Verifying Program Memory .......................................................... 12 Program Memory Writing Procedure .............................................................................................. 13 Program Memory Reading Procedure ............................................................................................. 14
4. ELECTRICAL SPECIFICATIONS ............................................................................................... 15 5. CHARACTERISTIC CURVE (REFERENCE VALUES) .............................................................. 21 6. APPLIED CIRCUIT EXAMPLE ................................................................................................... 22 7. PACKAGE DRAWINGS .............................................................................................................. 23 8. RECOMMENDED SOLDERING CONDITIONS .......................................................................... 24 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................... 25 APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 26
Data Sheet U14760EJ1V0DS00
5
PD6P5
1. PIN FUNCTIONS 1.1 Normal Operation Mode
Pin No. 1 2 15-20 Symbol KI/O0-KI/O7 Function These pins refer to the 8-bit I/O ports. I/O switching can be made in 8-bit units. In INPUT mode, a pull-down resistor is added. In OUTPUT mode, they can be used as a key scan output from key matrix. Refers to the input port. Can also be used as a key return input from key matrix. In INPUT mode, the availability of the pull-down resistor of the S0 and S1 ports can be specified by software in terms in 2-bit units. If INPUT mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state. Refers to the I/O port. In INPUT mode (S1), this pin can also be used as a key return input from key matrix. The availability of the pull-down resistor of the S0 and S1 ports can be specified by software in 2-bit units. In OUTPUT mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs the low level from the LED output synchronously with the REM signal. Refers to the infrared remote control transmission output. The output is active high. Carrier frequency: fX/8, fX/64, fX/96, high-level, fX/16, fX/128, fX/192 (usable on software) Refers to the power supply. These pins are connected to system clock ceramic resonators. Refers to the ground. Refers to the input port. The use of the STOP mode release of the S2 port can be specified by software. When using this pin as a key input from a key matrix, enable the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled, this pin can be used as the input port which does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) 11-14 KI0-KI3Note 2 These pins refer to the 4-bit input ports. They can be used as a key return input from key matrix. The use of the pull-down resistor can be specified by software in 4-bit units. -- Input (low-level) Output Format CMOS push-pullNote 1 When Reset High-level output
3
S0
--
High-impedance (OFF mode)
4
S1/LED
CMOS push-pull
High-level output (LED)
5
REM
CMOS push-pull
Low-level output
6 7 8 9 10
VDD XOUT XIN GND S2
-- -- -- --
-- Low level (oscillation stopped) -- Input (high-impedance, STOP mode release cannot be used)
Notes 1. Note that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when POC is released due to supply voltage startup.
6
Data Sheet U14760EJ1V0DS00
PD6P5
1.2 PROM Programming Mode
Pin No. 1, 2 15-20 3 CLK Clock input for updating address when writing/verifying program memory 6 VDD Power Supply. Supply +6 V to this pin when writing/verifying program memory. 7 8 9 10 XOUT XIN GND VPP Clock necessary for writing program memory. Connect 4 MHz ceramic resonator to these pins. GND Supplies voltage for writing/verifying program memory. Apply +12.5 V to this pin. 11-14 MD0-MD3 Input for selecting operation mode when writing/verifying program memory. Input Input - - - - Input Symbol D0-D7 Function 8-bit data input/output when writing/verifying program memory I/O I/O
Data Sheet U14760EJ1V0DS00
7
PD6P5
1.3 INPUT/OUTPUT Circuits of Pins
The input/output circuits of the PD6P5 pins are shown in partially simplified forms below. (1) KI/O0-KI/O7
VDD data Output latch
(4) S0
Input buffer
P-ch
output disable
N-chNote
OFF mode standby release
Selector
Input buffer
pull-down flag
N-ch
N-ch
(5) S1/LED
VDD
Note The drive capability is held low.
REM output latch P-ch
(2) KI0-KI3
standby release Input buffer
output disable standby release Input buffer
N-ch
pull-down flag
N-ch
pull-down flag
N-ch
(3) REM
VDD
(6) S2
standby release
P-ch data Output latch N-ch
Carrier generator
Input buffer
STOP release ON/OFF
N-ch
8
Data Sheet U14760EJ1V0DS00
PD6P5
1.4 Dealing with Unused Pins
The following connections are recommended for unused pins in the normal operation mode. Table 1-1. Connections for Unused Pins
Pin Connection Inside the Microcontroller KI/O INPUT mode OUTPUT mode REM S1/LED S0 S2 KI -- High-level output -- OUTPUT mode (LED) setting OFF mode setting -- -- Directly connect these pins to GND Outside the Microcontroller Leave open
Caution The I/O mode and the terminal output level are recommended to be fixed by setting them repeatedly in each loop of the program.
1.5 Notes on Using KI Pin at Reset
In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when POC is released due to supply voltage startup.
Data Sheet U14760EJ1V0DS00
9
PD6P5
2. DIFFERENCES AMONG PD64A, 65, AND PD6P5
Table 2-1 shows the differences among the PD64A, 65, and PD6P5. The only differences among these models are the program memory, supply voltage, system clock frequency, and oscillation stabilization wait time, and the CPU function and internal peripheral hardware are the same. The electrical characteristics also differ slightly. For the electrical characteristics, refer to the Data Sheet of each model. Table 2-1. Differences among PD64A, 65, and PD6P5
Item ROM
PD6P5
One-time PROM 2,026 x 10 bits
PD64A
Mask ROM 1,002 x 10 bits Ceramic oscillation 2.4 to 8 MHz
PD65
2,026 x 10 bits
Clock frequency
Ceramic oscillation 2.4 to 4.8 MHz
Oscillation stabilization wait time * On releasing STOP mode by release condition * At reset Supply voltage Electrical specifications 478/fX to 926/fX VDD = 2.2 to 3.6 V 246/fX to 694/fX VDD = 2.0 to 3.6 V 286/fX 52/fX
Some electrical specifications, such as data retention voltage and current consumption, differ. For details, refer to Data Sheet of each model.
10
Data Sheet U14760EJ1V0DS00
PD6P5
2.1 Program Memory (One-time PROM) ... 2,026 steps x 10 bits
This one-time PROM is configured with 10 bits per step and is addressed by the program counter. The program memory stores programs and table data. The 22 steps from addresses 7EAH through 7FFH constitute a test program area and must not be used. Figure 2-1. Program Memory Map
10 bits 000H
Page 0
3FFH 400H
Page 1
7E9H 7EAH 7FFH
Test program areaNote
Note Even if execution jumps to the test program area by mistake, it returns to address 000H.
Data Sheet U14760EJ1V0DS00
11
PD6P5
3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
The program memory of the PD6P5 is a one-time PROM of 2,026 x 10 bits. To write or verify this program memory, the pins shown in Table 3-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 3-1. Pins Used to Write/Verify Program Memory
Pin Name VPP VDD CLK MD0-MD3 D0-D7 XIN, XOUT Function Supplies voltage when writing/verifying program memory. Apply +12.5 V to this pin. Power supply. Supply +6 V to this pin when writing/verifying program memory. Inputs clock to update address when writing/verifying program memory. By inputting pulse four times to CLK pin, address of program memory is updated. Input to select operation mode when writing/verifying program memory. Inputs/outputs 8-bit data when writing/verifying program memory. Clock necessary for writing program memory. Connect 4-MHz ceramic resonator to this pin.
3.1 Operation Mode When Writing/Verifying Program Memory
The PD6P5 is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the PD6P5 has been in the reset status (VDD = 5 V, VPP = 0 V) for a specific time. In this mode, the operation modes shown in Table 3-2 can be set by setting the MD0 through MD3 pins. Connect all the pins other than those shown in Table 3-1 to GND via pull-down resistor. Table 3-2. Setting Operation Mode
Setting of Operation Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Clear program address to 0 Write mode Verify mode Program inhibit mode Operation Mode
x: don't care (L or H)
12
Data Sheet U14760EJ1V0DS00
PD6P5
3.2 Program Memory Writing Procedure
The program memory is written at high speed in the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the VDD pin. Keep the VPP pin low. Supply 5 V to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. Set the program memory address 0 clear mode by using the mode setting pins. Supply 6 V to VDD and 12.5 V to VPP. Set the program inhibit mode. Write data to the program memory in the 1-ms write mode. Set the program inhibit mode. steps (8) through (10). (11) Additional writing of (number of times of writing in (8) through (10): X) x 1 ms. (12) Set the program inhibit mode. (13) Input a pulse to the CLK pin four times to update the program memory address (+1). (14) Repeat steps (8) through (13) up to the last address. (15) Set the 0 clear mode of the program memory address. (16) Change the voltages on the VDD and VPP pins to 5 V. (17) Turn off power. The following figure illustrates steps (2) through (13) above.
Oscillation stabilization wait time
(10) Set the verify mode. If the data have been written to the program memory, proceed to (11). If not, repeat
Repeated X time Write Verify Additional write Address increment
Reset VPP VPP VDD GND VDD+1 VDD VDD GND CLK
D0-D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
Data input
Hi-Z
MD0
MD1
MD2
MD3
Data Sheet U14760EJ1V0DS00
13
PD6P5
3.3 Program Memory Reading Procedure
(1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the VDD pin. Keep the VPP pin low. Supply 5 V to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. Set the program memory address 0 clear mode by using the mode setting pins. Supply 6 V to VDD and 12.5 V to VPP. Set the program inhibit mode. Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. Set the program inhibit mode. (10) Set the program memory address 0 clear mode. (11) Change the voltage on the VDD and VPP pins to 5 V. (12) Turn off power. The following figure illustrates steps (2) through (10) above.
Oscillation stabilization wait time
Reset VPP VPP VDD GND VDD+1 VDD GND CLK
VDD
One cycle
D0-D7
Hi-Z
Data output
Data output
Hi-Z
MD0
MD1
"L"
MD2
MD3
14
Data Sheet U14760EJ1V0DS00
PD6P5
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25C)
Parameter Power supply voltage Symbol VDD VPP Input voltage Output voltage High-level output current VI VO IOHNote REM Peak value rms LED Peak value rms One KI/O pin Peak value rms Total of LED and KI/O pins IOL Note Peak value rms Low-level output current REM Peak value rms LED Peak value rms Operating ambient temperature Storage temperature TA Tstg KI/O, KI, S0, S1, S2 Conditions Rating -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150 Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
Note The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = -40 to +85 C)
Parameter Power supply voltage Symbol VDD Conditions fX = 2.4 to 4.8 MHz MIN. 2.2 TYP. 3.0 MAX. 3.6 Unit V
Data Sheet U14760EJ1V0DS00
15
PD6P5
DC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 3.6 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 Low-level input voltage VIL1 VIL2 VIL3 High-level input leakage current ILIH2 Low-level input leakage current ILIL1 ILIL2 ILIL3 High-level output voltage Low-level output voltage VOH1 VOL1 VOL2 High-level output current IOH1 IOH2 Low-level output current IOL1 ILIH1 S2 KI/O KI, S0, S1 S2 KI/O KI, S0, S1 KI VI = VDD, pull-down resistor not incorporated S0, S1, S2 VI = VDD, pull-down resistor not incorporated KI KI/O S0, S1, S2 VI = 0 V VI = 0 V VI = 0 V IOH = -0.3 mA IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V Built-in pull-down resistor R1 R2 Data hold power supply voltage Supply currentNote VDDDR IDD1 IDD2 IDD3 KI, S0, S1, S2 KI/O In STOP mode Operating mode HALT mode STOP mode fX = 4 MHz, VDD = 3 V 10 % fX = 4 MHz, VDD = 3 V 10 % VDD = 3 V 10 % VDD = 3 V 10 %, TA = 25C -5 -2.5 30 100 75 130 1.2 1.1 1.0 2.2 2.2 -9 -5 70 220 150 250 300 500 3.6 2.2 2.0 9.5 3.5 0.8 VDD 0.3 0.4 Conditions MIN. 0.8 VDD 0.65 VDD 0.65 VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2 VDD 0.3 VDD 0.15 VDD 3 3 -3 -3 -3 Unit V V V V V V
A A A A A
V V V mA mA
REM, LED, KI/O REM, LED KI/O REM KI/O KI/O
A A
k k V mA mA
A A
16
Data Sheet U14760EJ1V0DS00
PD6P5
AC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 3.6 V)
Parameter Instruction execution time KI, S0, S1, S2 high-level width Symbol tCY tH When canceling standby mode HALT mode STOP mode Conditions MIN. 13.3 10 10 Note TYP. MAX. 27 Unit
s s s s
Note 10 + 286/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillator frequency) POC Circuit (TA = -40 to +85 C)
Parameter POC-detected voltageNote Symbol VPOC Conditions MIN. TYP. 2.0 MAX. 2.2 Unit V
Note Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is canceled. From the time of VPOC VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 2.2 to 3.6 V)
Parameter Oscillator frequency (ceramic resonator) Symbol fX Conditions MIN. 2.4 TYP. 3.64 MAX. 4.8 Unit MHz
An external circuit example
XIN
XOUT Rd
C1
C2
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14760EJ1V0DS00
17
PD6P5
PROM Programming Mode DC Programming Characteristics (TA = 25C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V)
Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 30 30 MIN. 0.7 VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +13.5 V including overshoot. 2. Apply VDD before VPP and turn it off after VPP.
18
Data Sheet U14760EJ1V0DS00
PD6P5
AC Programming Characteristics (TA = 25C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V)
Parameter Address setup timeNote 1 (vs. MD0) MD1 setup time (vs. MD0) Data setup time (vs. MD0) Address hold timeNote 1 (vs. MD0) Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES tWAIT When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read 10 2 0 2 2 2 2 2 2 2 130 MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125 4.19 Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 1 1.0 1.05 21.0 130 TYP. MAX. Unit
s s s s s
ns
Data hold time (vs. MD0) MD0 data output float delay time VPP setup time (vs. MD3) VDD setup time (vs. MD3) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1) MD0 data output delay time MD1 hold time (vs. MD0) MD1 recovery time (vs. MD0) Program counter reset time CLK input high-, low-level width CLK input frequency Initial mode set time MD3 setup time (vs. MD1) MD3 hold time (vs. MD1) MD3 setup time (vs. MD0) AddressNote 1 data output delay time AddressNote 1 data output hold time MD3 hold time (vs. MD0) MD3 data output float delay time Reset setup time Oscillation stabilization wait timeNote 2
s s
ms ms
s s s s s s
MHz
s s s s s
ns
s s s
ms
Notes 1. The internal address signal is incremented at the falling edge of the third clock of CLK. 2. Connect a 4 MHz ceramic resonator between the XIN and XOUT pins.
Data Sheet U14760EJ1V0DS00
19
PD6P5
Program Memory Write Timing
tWAIT VPP VDD GND tRES tVPS
VPP
tVDS tXH
VDD+1 VDD VDD GND CLK
Hi-Z Hi-Z Hi-Z
D0-D7
tXL
Data input
Data input
Data output
Hi-Z
Data input
Hi-Z
tI MD0
tDS
tDH
tDV
tDF
tDS
tDH tAH
tAS
tPW MD1 tPCR MD2 tM3S MD3 tM1S tM1H
tM1R
tMOS
tOPW
tM3H
Program Memory Read Timing
tWAIT tRES tVPS VPP VPP VDD GND VDD+1 VDD VDD GND CLK tXL D0-D7 tI MD0
Hi-Z Data output
tVDS tXH
tDAD tHAD
Hi-Z Data output
tDV
tDFR tM3HR
MD1 tPCR MD2 tM3SR MD3
"L"
20
Data Sheet U14760EJ1V0DS00
PD6P5
5. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (fX = 4 MHz)
(TA = 25C ) 2 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 2 2.2 3 3.6 4 0 0.6 1.2 1.8 2.4 3 Power supply voltage VDD [V] Low-level output voltage VOL [V] HALT mode Operation mode
Low-level output current IOL [mA] Power supply current IDD [mA]
IOL vs VOL (REM, LED)
(TA = 25C, VDD = 3.0 V) 10 9 8 7 6 5 4 3 2 1
IOH vs VOH (REM)
(TA = 25C , VDD = 3.0 V) -20 -18
High-level output current IOH [mA] High-level output current IOH [mA]
IOH vs VOH (LED)
(TA = 25C , VDD = 3.0 V) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1
-16 -14 -12 -10 -8 -6 -4 -2 0 VDD VDD - 0.6 VDD - 1.2 VDD - 1.8 VDD - 2.4 VDD - 3 High-level output voltage VOH [V]
0 VDD
VDD - 0.6 VDD - 1.2 VDD - 1.8 VDD - 2.4 VDD - 3 High-level output voltage VOH [V]
IOL vs VOL (KI/O)
(TA = 25C, VDD = 3.0 V) -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 VDD
IOH vs VOH (KI/O)
(TA = 25C, VDD = 3.0 V)
280 240 200 160 120 80 40 0 0.6 1.2 1.8 2.4 3
High-level output current IOH [mA]
320
Low-level output current IOL [ A]
VDD - 0.6 VDD - 1.2 VDD - 1.8 VDD - 2.4 VDD - 3 High-level output voltage VOH [V]
Low-level output voltage VOL [V]
Data Sheet U14760EJ1V0DS00
21
PD6P5
6. APPLIED CIRCUIT EXAMPLE
Example of Application to System * Remote-control transmitter (48 keys; mode selection switch accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND S2Note Mode select switch
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 6 = 48 keys
Note S2: Set this pin to disable when releasing STOP mode. * Remote-control transmitter (56 keys accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND S2
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 7 = 56 keys
22
Data Sheet U14760EJ1V0DS00
PD6P5
7. PACKAGE DRAWINGS
20-PIN PLASTIC SSOP (7.62 mm (300))
20 11
detail of lead end F G T
P E 1 A H I S 10
L U
J
N C D
NOTE
S K
M
M
B
ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24+0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S20MC-65-5A4-2
Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
Data Sheet U14760EJ1V0DS00
23
PD6P5
8. RECOMMENDED SOLDERING CONDITIONS
Carry out the soldered packaging of this product under the following recommended conditions. For details of the soldering conditions, refer to information material Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than the recommended conditions, please consult one of our NEC sales representatives. Table 8-1. Soldering Conditions for Surface-Mount Type
PD6P5MC-5A4: 20-pin plastic SSOP (7.62 mm (300))
Soldering Method Infrared reflow VPS Soldering Condition Package peak temperature: 235 C, Time: 30 sec. Max. (at 210 C or higher), Count: three times or less Package peak temperature: 215 C, Time: 40 sec. Max. (at 200 C or higher), Count: three times or less Wave soldering Partial heating Solder bath temperature: 260 C Max., Time: 10 sec. Max., Count: once, Preheating temperature: 120 C Max. (package surface temperature) Pin temperature: 300 C Max., Time: 3 sec. Max. (per pin row) WS60-00-1 -- Recommended Condition Symbol IR35-00-3 VP15-00-3
Caution Do not use different soldering methods together (except for partial heating).
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Data Sheet U14760EJ1V0DS00
PD6P5
APPENDIX A. DEVELOPMENT TOOLS
A PROM programmer, program adapter, and emulator are provided for the PD6P5. Hardware * PROM programmer (AF-9706Note, AF-9708 Note, AF-9709Note) This PROM programmer supports the PD6P5. By connecting a program adapter to this PROM programmer, the PD6P5 can be programmed. Note These are products of Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (03-37331166). * Program adapter (PA-61P34BMC) It is used to program the PD6P5 in combination with AF-9706, AF-9708, or AF-9709. * Emulator (EB-65Note) It is used to emulate the PD6P5. Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Software * Assembler (AS6133) * This is a development tool for remote control transmitter software. Part Number List of AS6133
Host Machine PC-9800 series (CPU: 80386 or more) IBM PC/AT TM compatible OS MS-DOSTM (Ver. 5.0 to Ver. 6.2) MS-DOS (Ver. 6.0 to Ver. 6.22) PC DOSTM (Ver. 6.1 to Ver. 6.3) Supply Medium 3.5-inch 2HD 3.5-inch 2HC Part Number
S5A13AS6133 S7B13AS6133
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software.
Data Sheet U14760EJ1V0DS00
25
PD6P5
APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, please apply for a custom code at NEC. (1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.)
REM output 58.5 to 76.5 ms <1> 108 ms
<2>
108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1>
<3> REM output 9 ms 4.5 ms Custom code 8 bits Custom code' 8 bits Data code 8 bits 27 ms Data code 8 bits Stop bit 1 bit
13.5 ms Leader code
18 to 36 ms 58.5 to 76.5 ms
(3) Enlarged waveform of <3>
REM output 9 ms 13.5 ms 4.5 ms 0.56 ms 1.125 ms 2.25 ms 0 1
1
0
0
(4) Enlarged waveform of <2>
REM output 9 ms 11.25 ms Leader code 2.25 ms 0.56 ms Stop bit
26
Data Sheet U14760EJ1V0DS00
PD6P5
(5) Carrier waveform (Enlarged waveform of each code's high period)
REM output 8.77 s 26.3 s 9 or 0.56 ms Carrier frequency : 38 kHz
(6) Bit array of each code
C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
= = = = = = = =
C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C1 C2 C3 C4 C5 C6 C7
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data code as well) the total 32 bits of the 16-bit custom codes (Custom code, Custom code') and the 16-bit data codes (Data code, Data code) but also check to make sure that no signals are present.
Data Sheet U14760EJ1V0DS00
27
PD6P5
[MEMO]
28
Data Sheet U14760EJ1V0DS00
PD6P5
[MEMO]
Data Sheet U14760EJ1V0DS00
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PD6P5
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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Data Sheet U14760EJ1V0DS00
PD6P5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14760EJ1V0DS00
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PD6P5
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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